The present invention relates to an MOS semiconductor device in which a logic circuit having a low input resistance and a small drain capacitance is formed below a wide power supply wiring layer.
In an output circuit of an I/O (Input/Output) port of an LSI (Large Scale Integrated Circuit) in a microcomputer or the like, a buffer circuit for producing data outside the LSI is arranged. A transistor having a relatively high conductance is used for such an output buffer circuit since a large current of 1.6 mA flows to the buffer circuit at a low output voltage VOL of 0.4 V, for example. In an LSI for a microcomputer, a number of transistors having a relatively high conductance is used. An LSI of an 8-bit microcomputer having two I/O ports requires a total of 24 (8.times.3) output buffers (two I/O ports and one data bus port). Thus, the power supply line for all the I/O ports is a very wide metal wiring layer.
A power supply line comprising such a wide metal wiring layer increases the pattern area and is not preferable for an LSI. However, the use of a wide metal wiring layer as a power supply line cannot be avoided in view of the electrical characteristics as described above. For this reason, there is a demand to effectively utilize a region below such a wide power supply line. An example will be considered wherein an inverter is formed below a wide power supply line in a CMOS (Complementary Metal Oxide Semiconductor) integrated circuit.
FIG. 1 shows a CMOS inverter which is formed below a wide power supply line. Referring to FIG. 1, a first metal wiring layer 11 of aluminum or the like supplies a signal A, a second metal wiring layer 12 of aluminum or the like supplies a power supply voltage VDD, and a third metal wiring layer 13 of aluminum or the like is at ground potential. The third metal wiring layer 13 is formed in a very wide pattern. A p-type well region 14 is formed in an n-type semiconductor substrate 10. A source region 151 and a drain region 152 in the p-type well region 14 comprise an n.sup.+ -type diffusion layer. A source electrode S1, a gate electrode G1, and a drain electrode D1 are formed in the p-type well region 14. A source region 161 and a drain region 162 of a p.sup.+ -type diffusion layer are formed outside the p-type well region 14 on the semiconductor substrate 10. A source electrode S2, a gate electrode G2, and a drain electrode D2 are formed outside the p-type well region 14.
The gate electrodes G1 and G2 are connected to a first polycrystalline silicon layer 17 formed below the first through third metal wiring layers 11 to 13. The first polycrystalline silicon layer 17 is connected to the first metal wiring layer 11 through a contact hole C1. The drain electrode D1 is connected to a fourth metal wiring layer 18 of aluminum or the like through contact holes C2 and C3. The fourth metal wiring layer 18 is connected to an underlying second polycrystalline silicon layer 19 through a contact hole C4. An inverted signal A of the signal A supplied through the first metal wiring layer 11 is obtained from the second polycrystalline silicon layer 19. The source electrode S1 is connected to the third metal wiring layer 13 through a contact hole C5. The source electrode S2 is connected to the second metal wiring layer 12 through a contact hole C6. In this manner, a CMOS inverter for inverting the input signal A and producing an inverted signal A is obtained.
In the CMOS inverter shown in FIG. 1, the signal A is supplied to the gate electrodes G1 and G2 through the long, first polycrystalline silicon layer 17 below the third metal wiring layer 13. This is for reducing the areas of the drain regions 152 and 162 to decrease the output capacitance for high speed operation of the CMOS inverter. However, in the CMOS inverter shown in FIG. 1, since the first polycrystalline silicon layer 17 is long, the input resistance of the CMOS inverter is increased. This results in a lower operation speed of the CMOS inverter.
FIG. 2 shows a CMOS inverter wherein the length of the first polycrystalline silicon layer 17 shown in FIG. 1 is short to reduce the input resistance of the CMOS inverter. However, in this case, since the areas of drain regions 152 and 162 of the CMOS inverter increase, the junction capacitance of the drain is increased and the operation speed of the CMOS inverter is reduced. In FIG. 2, the same reference numerals as used in FIG. 1 denote the same parts.